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GS8160Z18/36T-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp Features
* NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs * 2.5 V or 3.3 V +10%/-10% core power supply * 2.5 V or 3.3 V I/O supply * User-configurable Pipeline and Flow Through mode * LBO pin for Linear or Interleave Burst mode * Pin compatible with 2M, 4M, and 8M devices * Byte write operation (9-bit Bytes) * 3 chip enable signals for easy depth expansion * ZZ Pin for automatic power-down * JEDEC-standard 100-lead TQFP package Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V tKQ tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) -250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.4 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns 280 330 275 320 5.5 5.5 175 200 175 200 255 300 250 295 6.0 6.0 165 190 165 190 230 270 230 265 6.5 6.5 160 180 160 180 200 230 195 225 7.0 7.0 150 170 150 170 185 215 180 210 7.5 7.5 145 165 145 165 165 190 165 185 8.5 8.5 135 150 135 150 mA mA mA mA ns ns mA mA mA mA
18Mb Pipelined and Flow Through Synchronous NBT SRAM
Functional Description
250 MHz-133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
The GS8160Z18/36T is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8160Z18/36T may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8160Z18/36T is implemented with GSI's high performance CMOS technology and is available in a JEDECStandard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock Address Read/Write
A R
B W QA
C R DB QA 1/26
D W QC DB
E R DD QC
F W QE DD QE
Flow Through Data I/O Pipelined Data I/O
Rev: 2.13a 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
(c) 1998, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8160Z18/36T-250/225/200/166/150/133 GS8160Z18T Pinout
VDDQ VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD VDD VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC
NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK W CKE G ADV A18 A17 A8 A9
A19 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC
Rev: 2.13a 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 2/26 (c) 1998, Giga Semiconductor, Inc.
GS8160Z18/36T-250/225/200/166/150/133 GS8160Z36T Pinout
DQC9 DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD VDD VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK W CKE G ADV A18 A17 A8 A9
DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9
Rev: 2.13a 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 3/26 (c) 1998, Giga Semiconductor, Inc.
GS8160Z18/36T-250/225/200/166/150/133 100-Pin TQFP Pin Descriptions
Symbol
A0, A1 A2-A18 A19 CK BA BB BC BD W E1 E2 E3 G ADV CKE NC DQA1-DQA9 DQB1-DQB9 DQC1-DQC9 DQD1-DQD9 ZZ FT LBO VDD VSS VDDQ
Type
In In In In In In In In In In In In In In In -- I/O I/O I/O I/O In In In In In In
Description
Burst Address Inputs; Preload the burst counter Address Inputs Address Input Clock Input Signal Byte Write signal for data inputs DQA1-DQA9; active low Byte Write signal for data inputs DQB1-DQB9; active low Byte Write signal for data inputs DQC1-DQC9; active low Byte Write signal for data inputs DQD1-DQD9; active low Write Enable; active low Chip Enable; active low Chip Enable; Active High. For self decoded depth expansion Chip Enable; Active Low. For self decoded depth expansion Output Enable; active low Advance/Load; Burst address counter control pin Clock Input Buffer Enable; active low No Connect Byte A Data Input and Output pins Byte B Data Input and Output pins Byte C Data Input and Output pins Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply
Rev: 2.13a 9/2002
4/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
GS8160Z18/36 NBT SRAM Functional Block Diagram
DQa-DQn
FT
Q
Write Data
K
Register 1
D
Write Data
Write Address
Burst Counter
K
Register 2
SA1' SA0'
Data Coherency
Read, Write and
D
K
K
Control Logic
SA1 SA0
K
Write Address
Register 1
Match
Q
LBO
K
FT
E1
E2
ADV
E3
Rev: 2.13a 9/2002
A0-An
5/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CKE
CK
BC
BD
W
BA
BB
G
Write Drivers
Memory Array
Register 2
K
Sense Amps
K
GS8160Z18/36T-250/225/200/166/150/133 Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable inputs will deactivate the device. Function Read Write Byte "a" Write Byte "b" Write Byte "c" Write Byte "d" Write all Bytes Write Abort/NOP W H L L L L L L BA X L H H H L H BB X H L H H L H BC X H H L H L H BD X H H H L L H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.
Rev: 2.13a 9/2002
6/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133 Synchronous Truth Table
Operation
Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Continue Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst NOP/Write Abort, Begin Burst Write Abort, Continue Burst Clock Edge Ignore, Stall Sleep Mode
Type Address
D D D D R B R B W B W B None None None None External Next External Next External Next None Next Current None
E1 E2 E3 ZZ ADV W Bx G CKE CK
H X X X L X L X L X L X X X X X L X H X H X H X H X X X X H X X L X L X L X L X X X L L L L L L L L L L L L L H L L L H L H L H L H L H X X X X X X H X H X L X L X X X X X X X X X X X L L H H X X X X X X L L H H X X X X X X L L L L L L L L L L L L H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X
DQ
High-Z High-Z High-Z High-Z Q Q High-Z High-Z D D High-Z
Notes
1
1,10 2 1,2,10 3 1,3,10 2,3
High-Z 1,2,3,10 High-Z 4
Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus will remain in High Z. 5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are Low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles.
Rev: 2.13a 9/2002
7/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Pipeline and Flow Through Read Write Control State Diagram
D
B
Deselect
R
W
D
D W R
R
New Read
B
New Write
W B
R
W
R
W
B
Burst Read
D
Burst Write
D
B
Key
Input Command Code
Notes:
1. The Hold command (CKE Low) is not shown because it prevents any state change.
Transition
Current State (n) Next State (n+1)
n n+1
2. W, R, B and D represent input command codes ,as indicated in the Synchronous Truth Table. n+2 n+3
Clock (CK)
Command
Current State
Next State
Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram
Rev: 2.13a 9/2002
8/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Pipeline Mode Data I/O State Diagram
Intermediate
BW High Z (Data In) D
R
Intermediate W Intermediate Intermediate
RB Data Out (Q Valid) D
Intermediate
W
R
High Z B D
Intermediate
Key
Input Command Code
Notes:
1. The Hold command (CKE Low) is not shown because it prevents any state change.
Transition
Current State (n)
Transition Next State (n+2)
Intermediate State (N+1)
2. W, R, B, and D represent input command codes as indicated in the Truth Tables.
n
n+1
n+2
n+3
Clock (CK)
Command
Current State
Intermediate State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 2.13a 9/2002
9/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Flow Through Mode Data I/O State Diagram
BW High Z (Data In) D RB W Data Out (Q Valid) D
R
W
R
High Z B D
Key
Input Command Code
Notes
1. The Hold command (CKE Low) is not shown because it prevents any state change.
Transition
Current State (n) Next State (n+1)
n n+1
2. W, R, B and D represent input command codes as indicated in the Truth Tables.
n+2
n+3
Clock (CK)
Command
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 2.13a 9/2002
10/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.
Mode Pin Functions Mode Name
Burst Order Control Power Down Control
Pin Name State
LBO ZZ L H L or NC H
Function
Linear Burst Interleaved Burst Active Standby, IDD = ISB
Note: There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 01 10 11 00 10 11 00 01 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 2.13a 9/2002
11/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it's internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
~~ ~ ~~ ~
tZZH
~~ ~~
CK ZZ
tZZS
tZZR
Sleep
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 2.13a 9/2002
12/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 to 4.6 -0.5 to 4.6 -0.5 to 6 -0.5 to VDDQ +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) +/-20 +/-20 1.5 -55 to 125 -55 to 125
Unit
V V V V V mA mA W
o
C
oC
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Rev: 2.13a 9/2002
13/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Power Supply Voltage Ranges Parameter
3.3 V Supply Voltage 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage
Symbol
VDD3 VDD2 VDDQ3 VDDQ2
Min.
3.0 2.3 3.0 2.3
Typ.
3.3 2.5 3.3 2.5
Max.
3.6 2.7 3.6 2.7
Unit
V V V V
Notes
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
VDDQ3 Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage
Symbol
VIH VIL VIHQ VILQ
Min.
2.0 -0.3 2.0 -0.3
Typ.
-- -- -- --
Max.
VDD + 0.3 0.8 VDDQ + 0.3 0.8
Unit
V V V V
Notes
1 1 1,3 1,3
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage
Symbol
VIH VIL VIHQ VILQ
Min.
0.6*VDD -0.3 0.6*VDD -0.3
Typ.
-- -- -- --
Max.
VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD
Unit
V V V V
Notes
1 1 1,3 1,3
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 2.13a 9/2002
14/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
TA TA
Min.
0 -40
Typ.
25 25
Max.
70 85
Unit
C C
Notes
2 2
Note: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Undershoot Measurement and Timing
VIH
Overshoot Measurement and Timing
20% tKC VDD + 2.0 V
VSS 50% VSS - 2.0 V 20% tKC
50% VDD
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters are sample tested.
Symbol
CIN CI/O
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
Package Thermal Characteristics Rating
Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP)
Layer Board
single four --
Symbol
RJA RJA RJC
Max
40 24 9
Unit
C/W C/W C/W
Notes
1,2 1,2 3
Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 2.13a 9/2002
15/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
VDD - 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2
Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table.
Output Load 1 DQ 50 VDDQ/2 * Distributed Test Jig Capacitance 30pF*
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage
Symbol
IIL IIN1 IIN2 IOL VOH2 VOH3 VOL
Test Conditions
VIN = 0 to VDD VDD VIN VIH 0 V VIN VIH VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDD IOH = -8 mA, VDDQ = 2.375 V IOH = -8 mA, VDDQ = 3.135 V IOL = 8 mA
Min
-1 uA -1 uA -1 uA -100 uA -1 uA -1 uA 1.7 V 2.4 V --
Max
1 uA 1 uA 100 uA 1 uA 1 uA 1 uA -- -- 0.4 V
Rev: 2.13a 9/2002
16/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Operating Currents
-250 Mode Symbol 0 to 70C -40 to 85C Unit 300 40 190 20 270 20 175 10 300 30 190 20 270 15 175 10 30 30 90 65 20 80 60 20 30 30 85 65 155 10 165 10 150 10 20 20 75 50 235 15 245 15 215 15 225 15 160 10 30 30 80 55 170 20 180 20 165 15 175 15 155 15 185 10 140 10 20 20 64 50 265 30 275 30 240 25 250 25 205 20 215 20 165 15 195 10 150 10 30 30 70 55 155 10 165 10 150 10 160 10 140 10 150 10 135 10 190 20 150 15 170 10 135 10 20 20 60 50 235 20 245 20 215 15 225 15 185 15 195 15 170 15 180 15 145 10 200 20 160 15 180 10 145 10 30 30 65 55 170 20 180 20 165 15 175 15 155 15 165 15 150 15 160 15 140 10 155 10 125 10 170 15 140 10 155 10 125 10 20 20 50 45 265 35 275 35 240 30 250 30 205 25 215 25 190 25 200 25 170 20 180 20 150 10 165 10 135 10 180 15 150 10 165 10 135 10 30 30 55 50
mA mA mA mA mA mA mA mA mA mA mA mA
-225 0 to 70C -40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C 0 to 70C 0 to 70C 0 to 70C 0 to 70C
-200
-166
-150
-133
Rev: 2.13a 9/2002 (x32/ x36) Flow Through Pipeline (x18) Flow Through IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ ISB 20 20 85 60 ISB IDD IDD 165 10 260 15 180 20 290 30 Pipeline Flow Through Pipeline (x18) Flow Through Pipeline -- Flow Through Pipeline -- Flow Through IDD 165 10 IDDQ IDD 260 20 IDD IDDQ 180 20 Pipeline IDD IDDQ 290 40 (x32/ x36)
Parameter
Test Conditions
Operating Current
3.3 V
Device Selected; All other inputs VIH or VIL Output open
17/26
Operating Current
2.5 V
Device Selected; All other inputs VIH or VIL Output open
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Standby Current
ZZ VDD - 0.2 V
Deselect Current
Device Deselected; All other inputs VIH or VIL
GS18/36-250/225/200/166/150/133
(c) 1998, Giga Semiconductor, Inc.
Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario.
GS8160Z18/36T-250/225/200/166/150/133 AC Electrical Characteristics
Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ1 tS tH tKC tKQ tKQX tLZ tS tH tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR
1
-250 Min 4.0 -- 1.5 1.5 1.2 0.2 5.5 -- 3.0 3.0 1.5 0.5 1.3 1.5 1.5 -- 0 -- 5 1 20 Max -- 2.5 -- -- -- -- -- 5.5 -- -- -- -- -- -- 2.3 2.3 -- 2.3 -- -- --
-225 Min 4.4 -- 1.5 1.5 1.3 0.3 6.0 -- 3.0 3.0 1.5 0.5 1.3 1.5 1.5 -- 0 -- 5 1 20 Max -- 2.7 -- -- -- -- -- 6.0 -- -- -- -- -- -- 2.5 2.5 -- 2.5 -- -- --
-200 Min 5.0 -- 1.5 1.5 1.4 0.4 6.5 -- 3.0 3.0 1.5 0.5 1.3 1.5 1.5 -- 0 -- 5 1 20 Max -- 3.0 -- -- -- -- -- 6.5 -- -- -- -- -- -- 3.0 3.2 -- 3.0 -- -- --
-166 Min 6.0 -- 1.5 1.5 1.5 0.5 7.0 -- 3.0 3.0 1.5 0.5 1.3 1.5 1.5 -- 0 -- 5 1 20 Max -- 3.4 -- -- -- -- -- 7.0 -- -- -- -- -- -- 3.0 3.5 -- 3.0 -- -- --
-150 Min 6.7 -- 1.5 1.5 1.5 0.5 7.5 -- 3.0 3.0 1.5 0.5 1.5 1.7 1.5 -- 0 -- 5 1 20 Max -- 3.8 -- -- -- -- -- 7.5 -- -- -- -- -- -- 3.0 3.8 -- 3.0 -- -- --
-133 Min 7.5 -- 1.5 1.5 1.5 0.5 8.5 -- 3.0 3.0 1.5 0.5 1.7 2 1.5 -- 0 -- 5 1 20 Max -- 4.0 -- -- -- -- -- 8.5 -- -- -- -- -- -- 3.0 4.0 -- 3.0 -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 2.13a 9/2002
18/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Pipeline Mode Read/Write Cycle Timing
1 CK
tS tH tKH tKL tKC
2
3
4
5
6
7
8
9
10
CKE
tS tH
E*
tS tH
ADV
tS tH
W
tS tH
Bn
tS tH
A0-An
A1
A2
A3
A4
tKQ tKQLZ tKQHZ
A5
tGLQV
A6
tKHQZ
A7
DQA-DQD
D(A1)
D(A2)
D (A2+1)
Q(A3)
Q(A4)
Q (A4+1)
D(A5)
Q(A6)
tS
tH
tOEHZ
tOELZ
tKQX
G
COMMAND
Write D(A1)
Write D(A2)
BURST Read Q(A3) Write D(A2+1)
Read Q(A4)
BURST Read Q(A4+1)
Write D(A5)
Read Q(A6)
Write D(A7)
DESELECT
DON'T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 2.13a 9/2002
19/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Pipeline Mode No-Op, Stall and Deselect Timing
1 CK
tS tH
2
3
4
5
6
7
8
9
10
CKE
tS tH
E*
tS tH
ADV
tS tH
W Bn
A0-An
A1
A2
A3
A4
A5 tKHQZ
DQ
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
tKQHZ
COMMAND
Write D(A1)
Read Q(A2)
STALL
Read Q(A3)
Write D(A4)
STALL
NOP
Read Q(A5)
DESELECT CONTINUE
DESELECT
DON'T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 2.13a 9/2002
20/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Flow Through Mode Read/Write Cycle Timing
1 CK
tS tH tKH tKL tKC
2
3
4
5
6
7
8
9
10
CKE
tS tH
E*
tS tH
ADV
tS tH
W
tS tH
Bn
tS tH
A0-An
A1
A2
A3
tKQ tKQLZ
A4
tKQHZ
A5
tGLQV tKHQZ
A6
A7
DQ
D(A1)
D(A2)
D (A2+1)
Q(A3)
Q(A4)
Q (A4+1)
D(A5)
Q(A6)
tS
tH
tOEHZ
tOELZ
tKQX
G
COMMAND
Write D(A1)
Write D(A2)
BURST Read Q(A3) Write D(A2+1)
Read Q(A4)
BURST Read Q(A4+1)
Write D(A5)
Read Q(A6)
Write D(A7)
DESELECT
DON'T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 2.13a 9/2002
21/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
Flow Through Mode No-Op, Stall and Deselect Timing
1 CK
tS tH
2
3
4
5
6
7
8
9
10
CKE E*
tS tH
tS tH
ADV
W
Bn
A0-An
A1
A2
A3
A4
A5 tKHQZ
DQ
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
tKQHZ
COMMAND
Write D(A1)
Read Q(A2)
STALL
Read Q(A3)
Write D(A4)
STALL
NOP
Read Q(A5)
DESELECT
CONTINUE DESELECT
DON'T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 2.13a 9/2002
22/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133 TQFP Package Drawing
L Symbol
A1 A2 b c D D1 E E1 e L L1 Y
c Pin 1
Description
Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle
Min. Nom. Max
0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 -- 0.45 -- -- 0 0.10 1.40 0.30 -- 22.0 20.0 16.0 14.0 0.65 0.60 1.00 -- -- 0.15 1.45 0.40 0.20 20.1 20.1 16.1 14.1 -- 0.75 -- 0.10
L1
e b
D D1
A1
Y
A2
E1 E
7
Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion.
BPR 1999.05.18
Rev: 2.13a 9/2002
23/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133 Ordering Information--GSI NBT Synchronous SRAM
Org
1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36
Part Number1
GS8160Z18T-250 GS8160Z18T-225 GS8160Z18T-200 GS8160Z18T-166 GS8160Z18T-150 GS8160Z18T-133 GS8160Z36T-250 GS8160Z36T-225 GS8160Z36T-200 GS8160Z36T-166 GS8160Z36T-150 GS8160Z36T-133 GS8160Z18T-250I GS8160Z18T-225I GS8160Z18T-200I GS8160Z18T-166I GS8160Z18T-150I GS8160Z18T-133I GS8160Z36T-250I GS8160Z36T-225I GS8160Z36T-200I GS8160Z36T-166I GS8160Z36T-150I GS8160Z36T-133I
Type
NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through
Package
TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP
Speed2 (MHz/ns)
250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5
TA3
C C C C C C C C C C C C I I I I I I I I I I I I
Status
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816Z36-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 2.13a 9/2002
24/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old; New GS18/36 1.00 9/1999A;GS18/ 362.0012/1999B GS18/362.00 12/1999BGS18/ 362.01 1/2000C Types of Changes Format or Content Content Page;Revisions;Reason * Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master File Rev B * Added x72 Pinout. * Added new GSI Logo * Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O supply; Completeness * Absolute Maximum Ratings; Changed VDDQ - Value: From: -.05 to VDD : to : -.05 to 3.6; Completeness. * Recommended Operating Conditions;Changed: I/O Supply VoltageMax. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to 3.6; Same page - took out Note 1;Completeness * Electrical Characteristics - Added second Output High Voltage line to table; completeness. * Note: There was not a Rev 2.02 for the 8160Z or the 8161Z. Content Content * Removed pin 14 from VSS in pin description table. * ADV changed to pin 85 in pin description table. * Changed the value of ZZ recovery in the AC Electrical Characteristics table on page 17 from 20 ns to 100 ns * Added 225 MHz speed bin * Updated Pg. 1 table, AC Characteristics table, and Operating Currents table to match 815xxx * Updated format to comply with Technical Publications standards * Updated Capitance table--removed Input row and changed Output row to I/O * Updated Features list on page 1 * Completely reworked table on page 1 * Updated Mode Pin Functions table on page 11 * Added 3.3 V references to entire document * Updated Operating Conditions table * Updated Operating Currents table and added note * Update table on page 1; added power numbers * Updated DQ on page 19 * Updated DQ on page 21 * Updated Pin Description table * Updated Operating Currents table
Format
GS18/362.0 1/2000DGS18/ 362.03 2/2000E
GS18/362.03 2/2000E; 8160Z18_r2_04 8160Z18_r2_04; 8160Z18_r2_05 8160Z18_r2_05; 8160Z18_r2_06 8160Z18_r2_06; 8160Z18_r2_07 8160Z18_r2_07; 8160Z18_r2_08 8160Z18_r2_08; 8160Z18_r2_09
Content
Content
Content
Content
8160Z18_r2_09; 8160Z18_r2_10
Content
* Updated table on page 1; updated power numbers * Updated Recommended Operating Conditions table (added VDDQ references)
Rev: 2.13a 9/2002
25/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8160Z18/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old; New Types of Changes Format or Content Page;Revisions;Reason
8160Z18_r2_10; 8160Z18_r2_11
Content
* Updated table on page 1 * Created recommended operating conditions tables on pages 13 and 14 * Updated AC Electrical Characteristics table * Updated Ordering Information for 225 MHz part (changed from 7ns to 6.5 ns) * Added 250 MHz speed bin * Deleted 180 MHz speed bin * Updated AC Characteristics table * Updated FT power numbers * Updated ZZ recovery time diagram * Updated Mb references from 16Mb to 18Mb * Updated AC Test Conditions table and removed Output Load 2 diagram * Removed Preliminary banner * Removed pin locations from pin description table
8160Z18_r2_11; 8160Z18_r2_12
Content
8160Z18_r2_12; 8160Z18_r2_13
Content
Rev: 2.13a 9/2002
26/26
(c) 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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